1. Field of the Invention
The present invention relates to a flip-flop circuit, and more particularly, it relates to a flip-flop circuit including latch circuits.
2. Description of the Background Art
A flip-flop circuit including various latch circuits is known in general. For example, Japanese Patent Laying-Open No. 8-279298 (1997) discloses such a flip-flop circuit.
FIG. 11 shows an exemplary conventional flip-flop circuit 101 having a structure similar to that of the aforementioned flip-flop circuit disclosed in Japanese Patent Laying-Open No. 8-279298. As shown in FIG. 11, the exemplary conventional flop-flop circuit 101 is constituted of two delay latch circuits 102a and 102b and an inverter circuit 103. The first-stage delay latch circuit 102a is constituted of a latch circuit 104 and a transfer gate transistor 105. The latch circuit 104 is constituted of two inverter circuits 106 and 107 and a transfer gate transistor 108.
Output terminals of the inverter circuits 106 and 107 are connected to input terminals of the inverter circuits 107 and 106 respectively. The output terminal of the inverter circuit 106 and the input terminal of the inverter circuit 107 are connected with each other through the transfer gate transistor 108 formed by a p-channel transistor 108a and an n-channel transistor 108b. A clock signal CLK and an inverted clock signal /CLK obtained by inverting the clock signal CLK by the inverter circuit 103 are input in the gates of the n-channel transistor 108b and the p-channel transistor 108a of the transfer gate transistor 108 respectively. Either the source region or the drain region of the transfer gate transistor 105 formed by a p-channel transistor 105a and an n-channel transistor 105b is connected to a node N101 between the input terminal of the inverter circuit 107 and the transfer gate transistor 108. A prescribed potential is input in either the drain region or the source region of the transfer gate transistor 105 from a node D. The clock signal CLK and the inverted clock signal /CLK obtained by inverting the clock signal CLK by the inverter circuit 103 are input in the gates of the p-channel transistor 105a and the p-channel transistor 105b of the transfer gate transistor 105 respectively.
The second-stage delay latch circuit 102b has a structure similar to that of the aforementioned first-stage delay latch circuit 102a. However, either the source region or the drain region of a transfer gate transistor 105 constituting the second-stage delay latch circuit 102b is connected to the node N102 of the first-stage delay latch circuit 102a between the input terminal of the inverter circuit 106 and the output terminal of the inverter circuit 107. Thus, a potential output from the node 102 of the first-stage delay latch circuit 102a is input in a node N103 through the transfer gate transistor 105 of the second-stage delay latch circuit 102b. 
An operation of the exemplary conventional flip-flop circuit 101 shown in FIG. 11 for introducing a potential Vdd received in the node D into the node N101 of the first-stage delay latch circuit 102a is now described. It is assumed that the flip-flop circuit 101 holds the potential of the node N101 at a level Vss through the output potential of the inverter circuit 106 before introducing the potential Vdd from the node D. In this case, the clock signal CLK first falls to the potential Vss. Thus, both of the p-channel transistor 105a and the n-channel transistor 105b of the transfer gate transistor 105 receiving the clock signal CLK and the inverted clock signal /CLK in the gates thereof respectively enter ON-states. Thus, the flip-flop circuit 101 inputs the potential Vdd of the node D in the node N101 through the transfer gate transistor 105. At this time, both of the n-channel transistor 108b and the p-channel transistor 108a of the transfer gate transistor 108 receiving the clock signal CLK and the inverted clock signal /CLK in the gates thereof respectively enter OFF-states. Thus, the flip-flop circuit 101 transmits no output potential (Vss) of the inverter circuit 106 the node N101, thereby not fixing the potential of the node N101 to the level Vss. Therefore, the flip-flop circuit 101 inhibits the potential Vdd of the node D and the potential of the node N101 (output potential of the inverter circuit 106) from colliding with each other when introducing the potential Vdd from the node D into the node N101. Thus, the flip-flop circuit 101 inhibits current consumption from increase resulting from collision between the potential Vdd of the node D and the potential of the node N101.
The exemplary conventional flip-flop circuit 101 shown in FIG. 11 is provided with the transfer gate transistor 108 formed by the p-channel transistor 108a and the n-channel transistor 108b for inhibiting the output potential of the inverter circuit 106 from transmission to the node N101 when introducing the potential of the node N into the node N101, in order to inhibit current consumption from increase resulting from collision between the potential of the node D and the output potential of the inverter circuit 106 (potential of the node N101). In the exemplary conventional flip-flop circuit 101, therefore, the circuit scale is disadvantageously increased due to the transfer gate transistor 108.